The present invention relates to the testing of processor-based systems. It particularly concerns a device for testing such systems by employing a memory-overlay technique.
Microprocessors and similar stored-program devices are widely employed for controlling systems of various types. In order to perform in-circuit tests of processor-controlled systems, it is ordinarily desirable for the testing device to sense the operations of various components of the system under test not only under ordinary processor control but also under the control of the test system.
One way to substitute a testing routine for the routine ordinarily executed by the processor is to provide a switching mechanism for connecting the processor to and disconnecting it from the processor-controlled components. Although arrangements of this type may be satisfactory in some circumstances, it is quite inconvenient in other circumstances to disconnect the microprocessor from the microprocessor-controlled components. Additionally, disconnecting the microprocessor alters the environment of the device under test, and certain defects that are only apparent when the processor is connected to the processor-controlled devices will not be detected. Furthermore, there are limits to the speed at which the processor can be switched into and out of the circuit. Too low a speed may cause the testing procedure to be intolerably long and, in fact, may make it impossible to test the system at the speed at which it is intended to operate.
Because of these drawbacks, another type of test system is often employed. In systems of this type, the processor remains in the circuit, but the test system includes connections that allow it to substitute its own instructions for the instruction that the microprocessor attempts to read from its program memory. This general approach is referred to as memory overlay.
An advantage of the memory-overlay technique is that it is ordinarily possible to substitute the test-system memory for the device-under-test memory at a speed faster than that at which complete connection and disconnection of the processor can be accomplished. A typical way to use the memory-overlay technique involves detecting commands from the processor directing the memory to place an instruciton on data lines of a bus connecting the memory to the processor. When such commands are detected, the test system drives the data lines with enough current to overcome those instruction signals and to substitute signals from the test-system memory. Such a technique results in considerable instantaneous power dissipation because the desired substitute-signal voltages have to be developed across the low output impedances of the memory bus drivers. Since any individual overdriving signal is present only for a very short time, no single overdriving signal will cause enough dissipation to damage the circuitry. But when such signals are applied repetitively, significant average power dissipation can result. To avoid the resulting thermal stresses, it is a design constraint on the test system that it avoid too-frequent repetition of overdriving signals. This can be an undesirable restriction.
Furthermore, although this technique results in significant speed advantages over complete disconnection of the processor from the processor-controlled devices, the use of large currents still restricts speed to some extent. The test system typically will need not only to substitute its instructions for some of the usual instructions on the data lines but also to sense the data-line contents when it allows the processor, the memory, or some other processor-controlled component of the system under test to place data on the data lines. Switching from the overdriving mode to the high impedance required for the sensing mode introduces delays that increase in duration with increases in the current required for overdriving.
An object of the present invention is to improve the memory-overlay technique by reducing power dissipation and permitting greater testing speed.